Exemplary embodiments of the present invention relate to a semiconductor package, and more particularly, to a semiconductor chip, which is applicable to a stack chip package, and a semiconductor package having a stack chip structure.
As the demands for small-sized, high-performance and mobile electronic products recently increase, ultra-small high-capacity semiconductor memory devices are increasingly demanded. In general, the storage capacity of the semiconductor memory device may increase by a method of increasing the integration degree of a semiconductor chip, or a method of mounting and assembling a plurality of semiconductor chips within a single semiconductor package. While the former method requires a lot of effort, capital, and time, the latter method can easily increase the storage capacity of the semiconductor memory by changing a packaging method. In addition, the latter method is very advantageous in terms of a necessary capital, research and development effort, and development time, as compared to the former method. Hence, semiconductor memory manufacturers are making many efforts to increase the storage capacity of the semiconductor memory device through a multi chip package which mounts a plurality of semiconductor chips within a single semiconductor package.
Examples of the method of mounting the plurality of semiconductor chips within the single semiconductor package include a method of mounting semiconductor chips horizontally, and a method of mounting semiconductor chips vertically. However, due to characteristics of electronic products seeking a miniaturization, most semiconductor memory manufacturers prefer a stack type multi chip package in which semiconductor chips are stacked vertically.
A stack chip package technique can reduce a manufacturing cost of a package due to a simplified process and is advantageous to mass production. However, the stack chip package technique may have a disadvantage in that an interconnection space for internal electrical connection of the package is insufficient due to increase in the number and size of stacked chips. That is, in such a state that a plurality of chips are attached to chip attachment regions of a substrate, a known stack chip package is manufactured in a structure in which a bonding wire of each chip and a conductive circuit pattern of a substrate are electrically connected by a wire. Thus, a space for wire bonding is required, and a circuit pattern area for wire connection is required. Consequently, a size of a semiconductor package may increase.
Considering these points, a package structure using a through-silicon via (TSV) has been proposed as an example of a stack package. Such a package is manufactured by forming TSVs within chips at a wafer level and coupling the chips physically and electrically in a vertical direction by the TSVs. A known manufacturing method will be described below.
FIG. 1 illustrates a process of forming a TSV. Referring to FIG. 1, vertical holes 5 are formed in regions adjacent to bonding pads 3 of each chip at a wafer (1) level, and an insulation layer (not shown) is formed on the surface of the vertical holes 5. Next, a seed metal layer is formed on the insulation layer. TSVs are formed by filling the vertical holes 5 with an electrolyte material, that is, a conductive metal 7, through an electroplating process.
A back grinding process is performed on the back side of the wafer to expose the conductive metal 7 filling the TSVs. The wafer is sawed into individual chips. Two or more chips are vertically stacked on the substrate so that signals can be transmitted and received through the conductive metal 7 of the TSVs. The top surface of the substrate, including the stacked chips, is molded, and solder balls are mounted on the bottom surface of the substrate. In this manner, the stack package may be manufactured.
When the chips with TSVs are stacked on the substrate, the individual chips are moved onto the substrate, for example, by a manufacturing equipment having a suction tool. Therefore, the align accuracy of the TSVs may become lowered. If warpage of the substrate occurs, it is more difficult to exactly align the TSVs. IF misalignment occurs between the TSVs or warpage of the substrate occurs, the conductive metals for transmitting and receiving signal may be broken or electrically shorted. Consequently, the chips may not operate normally.